Aspects of the present invention are directed to a schematic wire annotation tool for use in the design of integrated circuits and the design of interconnections between components.
An electrical network is an interconnection of electrical elements such as resistors, inductors, capacitors, transmission lines, voltage sources, current sources, and switches. An electrical circuit is a network that has a closed loop, giving a return path for the current. A network is a connection of two or more components, and may not necessarily be a circuit.
In designing an electrical circuit, it is typically necessary to optimize components and wire interconnects to achieve timing goals. With increasingly dense integrated circuits, the metal interconnects (wires) between components plays a more important role in determining speed of the circuits. One important aspect of circuit timing optimization is to assign to critical wires an appropriate width, spacing and metal layer. Early in the design, however, it is difficult to determine which nets are critical.
A common solution to timing problems is to use wide wires and wide spaces to improve the delay of the electrical signal through the interconnections. This also improves transition times of the signals on the wires and delays through components connected to the wire. Because wide wires and spaces add to routing congestion it is desirable to use minimal wire and spacing when possible and to restrict the use of wide wires and wide spacing for timing critical connections.
Known solutions to the problem of verifiably achieving optimal circuit timing with respect to wire widths, spacing and levels generally involve manual analyses of the nets in the schematic of an electrical circuit. A drawback of this approach is that it requires a significant investment of time and effort. Often multiple iterations of this manual flow are required to converge on a design that meets timing requirements.